At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform-for the better.
The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.The Opportunity
The infrastructure Processor Business Unit (IPBU) delivers hardware solutions in the networking space to various customers. All aspects of chip design from RTL design, DFT, verification and Physical Design is managed by teams across various sites around the world with close collaboration with each other.
- Execute and deliver block/chip level place and route from RTL to GDS for different Marvell IPBU products
- Track block and sub system level deliverables at various stages of the design cycle.
- Interact with FE/BE design teams to prepare good floorplan and suggest appropriate changes to achieve PPA goals
- Interact with design team to understand timing, CTS goals in detail to solve problems and propose physical design ideas.
- Debug timing constraint issues and feedback to design team.
- Debug LP issues and feedback to design team.
- Hands on experience and a solid understanding in all of the following physical design flows and methodologies: Synthesis/PnR, power/EM/IR analysis, power intent (UPF/CPF).
- BSEE or MS with 12+ years of experience in leading and managing physical design teams handling block level PNR from RTL to GDS as well as sub system/full chip timing and PV closure.
- Hands on experience running an industry standard EDA tools for running and debugging complex PNR issues in synthesis, PNR, STA and physical verification.
- Experience in tape-outs of high performance SOC is required.
- Understanding of several timing-related concepts is extremely desirable: setup, hold, clocking, timing corners, timing constraints, noise, and process variation.
- Physical design knowledge, from RTL to GDS tape out including floor planning, place and route, clock tree synthesis, timing closure and physical verification.
- Work with cross functional teams like Design, verification, DFT and post silicon validation to understand and implement the design requirements.
- Knowledge of scripting languages such as Perl/TCL is required.
- Diligent, detail-oriented, and should be able handle delegation of assignments efficiently.
- Must possess effective communication skills, self-driven individual and a good team player.
The Perks
With competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture. We’ll give you all the tools you need to succeed so you can grow and develop with us. For additional information on what it’s like to work at Marvell, visit our page.Your Future
Marvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance. If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
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