Job Description :
The customer develops advanced telecom systems with high data rates. You will be part of a team with responsibility for architectural and VHDL design, verification, layout and selection of technology and IP. Competence/Experience – Must have Long Experience of ASIC verification with Specman (e language, tools and methodology and building eVC’s) Long Experience from block level verification, functional verification, test coverage strategies Experience of functional coverage and building verification testbenches with Specman Experience of working with complex digital ASIC verification, verification of Traffic Management functionality Experience of design in VHDL Fluent in English (verbal and writing) Competence/Experience – Nice to have Experience of working with SystemVerilog, including building test benches Experience of constrained random verification, formal verification, e.g. using assertions and constraints Experience of SystemC, C, Tcl Experience from top level verification using TLM (transaction level model) Personality Self-motivated and driven, take initiative, open, see big picture, like challenges Social, team player Assignment info Location: onsite
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