The Opportunity
PHY BU

Essential Responsibilities (not limited to):

  • Responsible for understanding the logic, develop hitlist, verification environment, testcases etc., required for verifying the logic, individually
  • Document the verification plan and verification documentation
  • Develop Environment components, Code and Execute Tests
  • Run simulations and regressions
  • Analyze and improve functional coverage/code coverage
  • Participate and contribute in reviews
  • Report, track and close logic issues
  • Work and communicate effectively with global team

Preferred skills:

  • Experience in Multigigbit Ethernet Domain, PCS/MAC/TSN/PTP/MACSec
  • DSP Verification (Communication), Functional Safety (ISO26262) is a Plus
  • Background in SoC verification methodology and test bench development
  • Good programming skills desired, especially C++ and ARM assembly
  • IP architecture and verification knowledge
  • Formal Verification Experience is a Plus
  • Experience in scripting languages such as Perl, Python
  • Knowledge of Tools like Jenkins, Jira, Confluence
  • Gatelevel simulation and AMS simulation knowledge
  • Experience with Linux operating system
  • Experience with Cadence or any other industry tools
  • Demonstrates good analysis and problem-solving skills
  • Should be a good team player
  • Good communication skills and quick learning ability.
  • Knowledge of standard configuration management system git, perforce

Education:

  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience.
  • Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience.


Essential qualifications:

  • Must have good digital logic understanding and fundamentals of digital design.
  • Candidate must have excellent skills in digital logic verification and hardware description language (VHDL or Verilog),
  • Strong knowledge in object oriented programming using languages such as SystemVerilog
  • Must have hands on experience in hardware verification methodologies such as UVM or OVM,
  • Must be familiar with verification test planning and coverage driven verification closure, Verification strategies for directed and randomized testing and assertions
  • Must have good experience in using simulation tools and proficiency in simulation debug techniques.
  • Must have hands on knowledge on test-bench development and automation, bug tracking, and regression mechanisms

The Perks
With competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture. We’ll give you all the tools you need to succeed so you can grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
Your Future
Marvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance. If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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