Job Title: Sr. Application Engineer

Experience: 3 – 4 years
Location: Bangalore

Notice Period- With in 30days

Job Description:

Experience:

  • 3 to 4 years of experience in verification using VHDL/Verilog or Systemverilog
  • Preferably experience in supporting FPGA based emulation and prototyping solution
  • Experience in using FPGA/ASIC verification tools such as Questa, Riviera, VCS or NCSim or Vivado
  • Experience in using Linting tools
  • Overview about DO254 process for Avionics certification

Skills Requirement:

  • Good knowledge on FPGA based design flow
  • FPGA/SIC or SOC based design simulation and Verification
  • Good understanding of writing test benches based using VHDL, Verilog or SystemVerilog
  • Ability to take VHDL/Verilog design and run it simulation using verification tools such as Questa, Riviera or any other tool
  • Basic knowledge on ASIC Emulation and prototyping is added advantage.

Job Role:

  • Demonstrate the ASIC Front tools such as simulation, verification, emulation and Prototyping solution to MNCs and Indian Organizations
  • Carry out the evaluation of tools by taking customer and demonstrate benefits of ASIC frontend tools to target audience
  • Post Sales support of ASIC front end tools to target customers
  • Provide product training to target customers
  • Education: B.E. In Electronics and communication and finishing course in ASIC/SOC verification.


Source link