Job Description :
Skillset Must Have Block and Top level verification know-how Verification Plan Development Specman, eRM DDR2/DDR3 Testbench Development VHDL/Verilog simulation and debug End to End RTL Functional Verification Concepts Scripting Nice to have HVL: System Verilog is a Plus Understanding of SOC Subsystem Level Verification Experience Must have 5+ Years Of Experience Performing feature extraction from a specification Coverage closure Experience in Specman and eRM Nice to have Experience in SOC Block Level Verification Job Description Responsibilities Develop Verification Plan and Verification Architecture Develop Tests and Testbench Implement Functional Coverage Points Achieve 100% Functional Coverage Develop Verification Plan Documentation and Capture Results of Execution
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