- In this role, you will be part of the Central Engineering team playing a key role in delivering CMA (Compilable Memory Array) to the various products across the Marvell BUs.
- You will be responsible for the Verilog generation for compliable memories
- including the ability to allow for SDF back annotation and other EDA view generation such as CCS-NOISE and merge in with our normal timing/power LIBs,
- PWL to support Voltus (piece wise linear view of current, trigger files, etc.).
Education, Knowledge, Skills and Abilities:
- Bachelor’s or Master’s degree and/or PhD in Electrical/Electronic Engineering, Microelectronics or related fields with 6-10 years of related professional experience.
- Advanced knowledge of CAD design tools for building the test and verification environment
- Version control through GIT critical
- Java platform
- Required – Advanced software skills
- Preferred – Clojure and similar languages
- Hands on Timing rule generation u
- A good understanding of memories is extremely helpful
- Candidates should at least display a willingness to learn memories
- The Individual should be self motivated and/or work with the global teams
The Perks
With competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture. We’ll give you all the tools you need to succeed so you can grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
Your Future
Marvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance. If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
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