Staff/Senior/Lead/IC Engineer – Design Verification

Exp: 3-15Yrs

Job Description:
Design Verification
· Self-starter with 3+ years of relevant experience on IP / Sub-system verification on multi million Gate and complex Design with multiple clocks with minimal supervision
· Hands on knowledge with strong fundamentals of SV/ UVM (and Verilog) and ability to modify or develop checkers, monitors etc. from scratch. (Must have).
· Ability to debug Test bench and RTL issues and handle legacy Testbench and make enhancements.
· Highly desirable experience in IP with system interface protocols like AMBA /AHB or AXI.
· Must have experience in end to end IP verification project cycle, including Testbench Strategies, TB development, simulation debugging.

If interested please forward your updated CV to [HIDDEN TEXT]


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