Position: ASIC Verification Engineer

Experience: 4+ Yrs

Notice Period: Immediate / 15 days

JD

– 3 to 4 years of experience in System Verilog HVL.

– 2 to 3 years of experience in UVM.

– Experience in protocols like Ethernet, PCIe, MIPI, USB or similar

– Experience has executed at-least 2 SoC Verification project.

– Expertise in IP as well as SOC verification

– Experience of developing assertion, checkers, coverage and scenario creation.


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