Location : Hyderabad
This position is a permanent position with our client (US Based Semiconductor Product Company with revenue more than 30 Billion USD) Our client is a world leader (Top5 Semicon Company in 2018) in innovative memory solutions that transform how the world uses information.
They have over 34,000 team members in 17 countries who work with the worlds most trusted brands, delivering memory and storage systems for a broad range of applications and sparking countless possibilities in technology
Seeking an ASIC Architect for clients ASIC architecture team. You should have strong knowledge and experience with all aspects of the SOC design and implementation flow including coverage driven verification, synthesis, P&R, STA, DFT, power-islands, floor-planning, CTS, IR-drop and an understanding of how architecture decisions impact these flows.
You will be responsible for developing, contributing, and leading ASIC macro and micro-architecture activities in our storage-based controllers.
You should be highly motivated with strong communication skills, attention to detail, and quality oriented.
Candidates with a take-ownership attitude will succeed in this role. Responsibilities include, but not limited to: Reviewing product and FW requirements Working with other ASIC architects and with system architects to define and document the feature sets and data/control flows implemented by the controller and each of its component IPs Defining requirements for ASIC design, verification, and physical implementation teams Evaluating area, performance, power, and ease-of-implementation trade-offs between different implementation solutions Reviewing and configuring 3rd party IPs Supporting other teams in the ASIC organization and reviewing their work Supporting product teams with documentation, code-reviews, and silicon debug Continuously finding opportunities for improving design quality and design practices
Minimum Qualifications: Bachelor degree in Engineering but Master degree preferred 10+ years of ASIC architecture experience with strong knowledge of PCIe + NVMe and/or UFS in a storage application RTL design experience in Verilog/SystemVerilog Knowledge and experience in various aspects of SOC design, verification, and implementation flows Experience with low-power design techniques Scripting and Unix shell language experience: e.g. Perl, Python, Unix shell scripts Ability to read and understand SW code Understanding of CPU and memory architectures, datapath pipelining mechanisms, distributed system design, ASIC low-power implementations, clock and reset methodologies Preferred Skills: Experience with HW modeling languages ASIC architecture experience in NAND based storage products (e.g. SSD, eMMC, UFS, USB) Design/architecture experience with high-speed serial and parallel interfaces (e.g. PCIe, MIPI, DDR, LPDDR, ONFI) Design/architecture experience with NVMe and/or UFS host protocols Familiarity with automotive design and qualification processes are a bonus
Contact: Uday Bhaskar
Mulya Technologies
“Mining the Knowledge Community”
Email id : [HIDDEN TEXT]
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