About Marvell
At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform-for the better.
The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.The Opportunity
The infrastructure Processor Business Unit (IPBU) delivers hardware solutions in the networking space to various customers. All aspects of chip design from RTL design, DFT, verification and Physical Design is managed by teams across various sites around the world with close collaboration with each other.
Responsibilities:

  • Execute and deliver block/chip level place and route from RTL to GDS for different Marvell BU products.
  • Interact with FE/BE design teams to prepare good floorplan and suggest appropriate changes to achieve PPA goal.
  • Interact with design team to understand timing, CTS goals in detail to solve problems and propose physical design ideas
  • Debug timing constraint issues and feedback to design team
  • Debug LP issues and feedback to design team
  • Setup and Run physical design steps Floorplan, PG Mesh Creation, Placement, CTS, Routing optimizations to achieve PPA goal
  • Check Logic equivalence from pre layout to post layout netlist
  • Analyze timing within PD environment and using STA tools and achieve timing closure by generating and applying ECOs to layout
  • Interact with PV team to analyze DRC/LVS/ANT/ERC results and achieve PV closure
  • Analyze results from PGV, fix IR drop issues and achieve closure
  • Develop perl/tcl scripts for generic tasks as required

Required Skills:

  • 8 to 10 years of experience in block/chip level Physical Design execution
  • Good understanding and hands on experience in physical design tasks Floor-planning, PG mesh creation, placement, CTS and Routing for complex blocks
  • Good knowledge on timing constraints, static timing analysis, debug problems and closure
  • Good knowledge on DRC/LVS/ANT/ERC issues and closure
  • Good knowledge on IR drop, ESD, EM issues and fixes
  • Good knowledge on low power concepts and application to PD
  • Experience with cutting edge technology node designs like 16nm, 12nm, 7nm
  • Ability to plan and work independently and coordinate with cross functional teams
  • Scripting skills using perl/tcl
  • Good communication skills and ability work as a team
  • Hands on expertise with industry standard EDA tools including but not limited to Design Compiler/RTL Compiler, Innovus/ICC2, Primetime/Tempus, QRC/StarXT, Calibre

**Education Qualification: BE/BTech/ME/MTech/ in E&C, EEE from the reputed institutionThe Perks
With competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture. We’ll give you all the tools you need to succeed so you can grow and develop with us. For additional information on what it’s like to work at Marvell, visit our page.Your Future
Marvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance. If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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