Job Description :
Cyient is a global engineering and technology solutions company.As a Design, Build, and Maintain partner for leading organizations worldwide, we take solution ownership across the value chain to help clients focus on their core, innovate, and stay ahead of the curve. We leverage digital technologies, advanced analytics capabilities, and our domain knowledge and technical expertise, to solve complex business problems.
With over 15,000 employees globally, we partner with clients to operate as part of their extended team in ways that best suit their organization’s culture and requirements. Our industry focus includes aerospace and defence, healthcare, telecommunications, rail transportation, semiconductor, geospatial, industrial, and energy.
Job Description
Cyient is a global engineering and technology solutions company.As a Design, Build, and Maintain partner for leading organizations worldwide, we take solution ownership across the value chain to help clients focus on their core, innovate, and stay ahead of the curve. We leverage digital technologies, advanced analytics capabilities, and our domain knowledge and technical expertise, to solve complex business problems.
With over 15,000 employees globally, we partner with clients to operate as part of their extended team in ways that best suit their organization’s culture and requirements. Our industry focus includes aerospace and defence, healthcare, telecommunications, rail transportation, semiconductor, geospatial, industrial, and energy.
Job Description
- Experience of 3 year to 5 years in Analog / Mixed Signal /SERDES Layout.
- Able to execute on any Analog / Mixed Signal module layout activity (i.e. from schematics2 clean GDSII)
- Good working experience in Cadence Virtuoso Layout Editor, Mentor Caliber etc.
- Must have experience in AMS layout porting from x nm to 10/7/5/3nm process nodes.
- Process node experience of 180nm to 3nm
- Hands on Experience in Block Level, Module Level Layouts
- Must have hands on experience in MIPI/LPDDR/SERDES modules.
- Performing various kinds of Analog layouts, implementations from floor planning down to complex block level layouts.
- Should have sound knowledge on tackling DRC/LVS/Antenna/LPE Checks of Analog Layout Verification
- Good understanding of CMOS/BiCMOS/SOI/FinFet process
- Knowledge of various analog layout techniques, understanding of various circuit principles as affected by Layouts such as speed, capacitance, power, noise, and area.
- Responsible for timely and quality execution of layout design.
- Good communication skills and proactive at work.
Skills & ExperienceCadence Virtuoso, Cadence Virtuoso Layout Suite, Virtuoso, Virtuoso XL
Cyient is an Equal Opportunity Employer.
Cyient recruits, employs, trains, compensates, and promotes regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender, gender identity or expression, veteran status, and other protected status as required by applicable law. We are proud to be a diverse and inclusive company where our people can focus their whole self on solving problems that matter.
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