NVIDIA is seeking a motivated memory subsystem architects to work with a team to solve complex problems while optimizing performance, area, complexity, and power on leading-edge SoC systems. This team helps build new and innovative products tailored to NVIDIA’s world changing solutions for autonomous vehicles, mobile systems, deep-learning, and gaming.
What you will be doing:

  • Developing architecture and micro-architecture to improve the state-of-the-art in memory system optimizing along the axes of performance, power efficiency, complexity, area, effort, and schedule.
  • Performance modeling and simulation of features to improve memory system efficiency.
  • Implementing and maintaining high-level performance and functional models.
  • Analyzing benchmarks, application workloads, and performance simulation results to identify tradeoffs in areas of micro-architectural optimizations.
  • Debugging performance and functional issues with high-level models, RTL simulation, and silicon.
  • Working with various cross functional teams like ASIC design and verification, software, product development team, marketing in developing the comprehensive solution.

What we need to see:

  • Master degree or equivalent experience in Electrical Engineering, Computer Science, Computer Engineering or related field (or the equivalent experience).
  • 6+ years of meaningful work experience in SoC Architecture and development specifically in one or more domains of MMU and address translation, memory caching, interconnects, and DRAM controllers.
  • Strong communication and interpersonal skills are required along with the ability to work in a dynamic, product oriented, distributed team.

Ways to stand out from the crowd:

  • Practical experience with MMU and address translation performance modeling and analysis.

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