Senior Engineer/Staff Engineer – DFT
EXP: 8-15
Location: Pune.
Role and Responsibility :
Capability to lead a project for DFT full chip activity and for block level closure

Develop architecture and implementation for new DFT features, enhancing existing features , bug fixing
Work on latest technology & synopsis tool flow wrt DFT implementation, ATPG and DFT verification

Optimizing test time, test area and test power and coverage improvement to enhance performance
Trouble shooting and solving issues/bugs reported by peer or by customer
Able to support Juniors for their development , and collaborate with them for project work.
Requirements :
Excellent DFT skill wrt scan/compression, JTAG and MBIST

Strong knowledge on Scan/compression/wrapper/OCC implementation, ATPG and DFT verification
Good understanding and proven project experience on pattern generation(SA & TDF), low power ATPG, SDD, Burn-in and ATE debugging capability
Proven experience on coverage improvement and pattern reduction
Proven experience on GATE level simulation with and without SDF
Should have worked on full chip level and also block level DFT closure
Understanding on SDC constraint, DFT STA, Linting, formality and DFT rule check will be add on to suitability
Proven experience on Synopsys tool flow for implementation and ATPG wrt full chip level work

Familiar with checkin/Checkout database and Bug filing and tracking and documentation
Must have effective interpersonal and teamwork skills to take care Junior folks
Excellent communication skills to communicate the project issues and solution across global team
Must have the ability to multi-task in a fast-paced environment to meet the dead line
Skills: DFT, ATPG, Scan Insertion.

Interested candidates may send the updated cv to jancyATpeopleplusindiaDOTcom to discuss.


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